Course Description
Computer architecture deals with the art and science of designing and integrating hardware subsystems, spanning the hardware/software interface, to create a computer system that achieves functional correctness and meets design objectives in performance, power, energy, and cost. This course provides in-depth coverage of modern computer systems, with a special focus on Systems-on-Chip (SoCs) for mass-market mobile and edge computing devices, including smartphones, tablets, and diverse smart home/office devices. Topics span the design and evaluation of three major subsystems: (1) the processing subsystem -- superscalar out-of-order cores, multicore processors, asymmetric and heterogeneous cores, and AI/DL accelerators; (2) the memory subsystem -- main memory and DRAM, multicore cache hierarchies, and co-processor shared memory management; and (3) the interconnect subsystem -- Network on Chip (NoC), multi-die packages, and chiplets. Each subsystem is studied from the perspective of several first-class design goals: performance, power consumption, and energy efficiency. The course places strong emphasis on professional design tools (architecture/microarchitecture simulators, RTL design and synthesis, area/power/thermal modeling) and on hands-on experimentation with physical hardware, with the goal of preparing students to be highly competent processor designers and computer architects in industry.
Recommended pre/co-requisites: 15-513/18-613; 18-447 (or a course based on Computer Organization and Design by Patterson & Hennessy). Verilog and gem5 experience would be very helpful.
For course details, e.g., office hours and grading, see the Course Info page. Lab descriptions are on the Labs page.
Schedule
| Week | Date | Class Activity | Readings | Assignments |
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| Lab 0: Orientation (1 week) | ||||
| Week 1 | Aug 25 (Tue) | Lecture 1: Computer Architecture & Processor Design [JS/OH] |
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| Aug 27 (Thu) | Lecture 2: Modern Superscalar Out-of-Order Processors [JS] | |||
| Aug 28 (Fri) | Recitation 1: Course Overview; Lab 0 & Lab 1 Assignments | |||
| Lab 1: CPU Design: Dynamic Branch Predictors (2 weeks) | ||||
| Week 2 | Sep 1 (Tue) | Lecture 3: Advanced Dynamic Branch Prediction Techniques [JS] |
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| Sep 3 (Thu) | Lecture 4: Instruction Fetch and Decode Techniques [JS] | |||
| Sep 4 (Fri) | Recitation 2: Ensure Team Formations & Discussion of Modern Superscalar Out-of-Order Processors | |||
| Week 3 | Sep 8 (Tue) | Lecture 5: Register Renaming & Out-of-Order Execution [JS] |
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| Sep 10 (Thu) | Lecture 6: Dynamic Instruction Scheduling Techniques [JS] | |||
| Sep 11 (Fri) | Recitation 3: Lab 2 Preview & Tomasulo’s Algorithm | |||
| Lab 2: CPU Design: Superscalar Out-of-Order Structures / Cache Coherence (4 weeks) | ||||
| Week 4 | Sep 15 (Tue) | Lecture 7: Dealing with Long Latency Memory Instructions [OH] |
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| Sep 17 (Thu) | Lecture 8: Modern Memory Hierarchy & Data Storage [OH] | |||
| Sep 18 (Fri) | Recitation 4: Cache Coherence, Memory Consistency, Asym. Cores | |||
| Week 5 | Sep 22 (Tue) | Lecture 9: System Level Memory Prefetching Techniques [TH/LC] |
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| Sep 24 (Thu) | Lecture 10: Operating System & Runtime Environment [SM/LC] | |||
| Sep 25 (Fri) | Recitation 5: Operating Systems and Prefetching | |||
| Week 6 | Sep 29 (Tue) | Lecture 11: Cache Coherence & Memory Consistency [OH] |
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| Oct 1 (Thu) | Lecture 12: Parallel Programming & Threading Models [OH] | |||
| Oct 2 (Fri) | Recitation 6: Memory Consistency and Parallel Programming | |||
| Week 7 | Oct 6 (Tue) | MIDTERM EXAM #1 |
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| Oct 8 (Thu) | Lecture 13: GPU and TPU for Accelerating Workloads [OH] | |||
| Oct 9 (Fri) | Recitation 7: Accelerator Architectures & Lab 3 Logistics (Async) | |||
| 10/12-10/16 NO CLASSES - Fall Break!!! | ||||
| Lab 3: Heterogeneous Cores: Profiling Snapdragon SoC (4 weeks) | ||||
| Week 8 | Oct 20 (Tue) | Lecture 14: Modern Heterogeneous Architectures [OH] |
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| Oct 22 (Thu) | Lecture 15: Research on Sparse Tensor Compilation and Mapping for Heterogeneous Domain-Specific Accelerators [OH] | |||
| Oct 23 (Fri) | Recitation 8: Exam 1 Post Mortem & Unified Memory & Dataflow | |||
| Week 9 | Oct 27 (Tue) | Lecture 16: Performance, Power, Energy Efficiency Iron Laws [JS] |
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| Oct 29 (Thu) | Lecture 17: (Re)Emergence of VLIW in NPU and LPU Designs [JS] | |||
| Oct 30 (Fri) | Recitation 9: VLIW & Power/Efficiency | |||
| Week 10 | Nov 3 (Tue) | NO CLASS - Democracy Day |
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| Nov 5 (Thu) | Lecture 18: Return of the CPU? Overview of NVIDIA Vera CPU [JS] | |||
| Nov 6 (Fri) | Recitation 10: CPU Re-emergence / Lab Assistance | |||
| Week 11 | Nov 10 (Tue) | Lecture 19: Experimental Characterization of LLM Inference on Heterogeneous (Edge & Server) Systems [JS] | ||
| Nov 12 (Thu) | Lecture 20: Neuromorphic & NeuroAI Computing Systems [JS/LC] | |||
| Nov 13 (Fri) | Recitation 11: Neuromorphic Computing | |||
| Lab 4: Heterogeneous Cores: Heterogeneous Systems and Algorithms (3.5 weeks) | ||||
| Week 12 | Nov 17 (Tue) | MIDTERM EXAM #2 | ||
| Nov 19 (Thu) | Lecture 21: Special Guest #1 Career Story of a Computer Architect [Bryan Black - Moto, Intel, AMD, Chipletz (CMU alum)] | |||
| Nov 20 (Fri) | Recitation 12: Lab Assistance & Exam #2 Post Mortem | |||
| Week 13 | Nov 24 (Tue) | NO CLASS | ||
| Nov 26 (Thu) | NO CLASS - Thanksgiving Holiday | |||
| Nov 27 (Fri) | NO CLASS - Thanksgiving Holiday | |||
| Week 14 | Dec 1 (Tue) | Lecture 22: Special Guest #2 Career Story of a Computer Architect [Trung Diep - Intel, Rambus, Marvell (CMU alum)] |
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| Dec 3 (Thu) | Lecture 23: Special Guest #3 Career Story of a Computer Architect [Bob Rychlik - Intel, Qualcomm (CMU alum)] | |||
| Dec 4 (Fri) | Recitation 13: Lab Assistance & Course Wrapup | |||